Mentor Graphics Enables Hardware/Software Co-Verification with StarCore Processor Models
SANTA CLARA, Calif.—(BUSINESS WIRE)—Sept. 28, 2004—
Mentor Graphics Corp. (Nasdaq:MENT) today announced a
technical collaboration with StarCore to offer Seamless(R)
hardware/software co-verification processor models for StarCore's
licensable processor cores, SC1200 and SC1400.
Developed to allow systems designers using Mentor's
industry-leading Seamless co-verification environment to quickly
incorporate StarCore processor subsystems into their designs, the
support packages implement SC1200 and SC1400 cores and subsystems, as
well as providing performance profiling for cache activities, memory
accesses and software codes.
The StarCore model, when used with the Mentor Graphics(R) Seamless
co-verification environment, enables software/hardware development in
parallel, removing software from the critical path, reducing the risk
of hardware iterations and increasing overall product quality. With
increased visibility into a hardware design, designers can debug
designs while they are exercised by production software running on the
CPU.
"The Seamless hardware/software co-verification StarCore Processor
Support Packages for SC1200 and SC1400 can help organizations
significantly improve time-to-market by allowing them to develop in
software before creating physical hardware," said Alex Bedarida, vice
president of marketing and sales, StarCore. "Mentor Graphics is a
known leader in the hardware/software co-verification space, and we
are pleased to offer our customers this important and cost-saving
package."
"Optimizing the performance of key software algorithms is critical
for DSP system development," said Serge Leef, general manager, SoC
Verification Division, Mentor Graphics. "The performance profiling
features of Seamless and the StarCore Processor models provide an
early, accurate analysis, ensuring confidence that specifications are
being met."
Pricing and Availability
The Seamless hardware/software co-verification StarCore Processor
Support Packages for SC1200 and SC1400 cores and subsystems are
available now. More information is available at
www.mentor.com/seamless.
About Seamless
Linking popular software development and debug tools with logic
simulation, the Seamless environment delivers high performance
co-verification months before a hardware prototype can be built. The
Seamless environment enables software and hardware development to be
parallel activities, removing software from the critical path and
reducing the risk of hardware prototype iterations resulting from
integration errors. User-controlled optimizations boost performance by
isolating the logic simulator from software-intensive operations such
as block memory transfers and algorithmic routines.
About Mentor Graphics
Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in
electronic hardware and software design solutions, providing products,
consulting services and award-winning support for the world's most
successful electronics and semiconductor companies. Established in
1981, the company reported revenues over the last 12 months of about
$675 million and employs approximately 3,800 people worldwide.
Corporate headquarters are located at 8005 S.W. Boeckman Road,
Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are
located at 1001 Ridder Park Drive, San Jose, California 95131-2314.
World Wide Web site: www.mentor.com.
Mentor Graphics and Seamless are registered trademarks of Mentor
Graphics Corporation. All other company and/or product names are the
trademarks and/or registered trademarks of their respective owners.
Contact:
Mentor Graphics
Larry Toda, 503-685-1164
larry_toda@mentor.com
or
Weber Shandwick
Hayley Luz, 503-552-3726
hluz@webershandwick.com
